Disk Drives commonly employ one or more microprocessors or microcontrollers (the terms are used interchangeably) in an embedded control system to control operations of the drive. In order to maximize the performance of the microprocessor, a cache control system is frequently included which minimizes the access time for fetching instructions and data from memory.
As is well known in the art, a cache system depends on locality of reference to provide the expected performance improvement. This means that the memory address range for a particular segment of program code being executed tends to be co-extensive with the range of memory data being stored in the cache. Therefore most accesses after the cache is initially loaded will be in the cache—i.e. a cache “hit”. When a memory access address falls outside the cached segment, i.e. a “cache miss” occurs, the cache control system directs the access to main memory and store the new data in the cache. Generally, when a cache miss occurs, the cache control system fetches a string or burst of data sequential to the miss address, anticipating that subsequent requests will be sequential. Because the cache memory in most embedded systems is quite small, the cache miss generally causes most, if not all, of the existing cached data to be replaced by the fetched burst of sequential data.
Unfortunately, in many instances, a cache miss may occur because the program is fetching an operand which is outside the range of the executing code segment, even though the code segment continues to be executed. This can result in severe “thrashing” of data in the cache thereby diminishing or losing the benefit of the cache system.
In prior art cache systems, a so-called “Harvard” architecture has been used which attempts to solve the foregoing problem by providing separate cache structures for instructions and data. Unfortunately, the Harvard architecture is more complex and may unduly increase die size and cost in integrated circuits commonly used for disk drive embedded control systems.
Accordingly, what is needed is an improved disk drive cache control system which provides beneficial cache performance without incurring cost penalties in an integrated circuit.